Basic
CPU architecture
The instruction set and internal organization of a processor, such as Xtensa or RISC-V.
In industrial practice
It determines tools, compatible libraries, performance and firmware lifetime.
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TECHNICAL GLOSSARY
Processing
Architecture, cores, clock and ultra-low-power coprocessors: what defines performance, compatible tools and firmware lifetime.
terms in this category
Intermediate
RISC-V
An open instruction-set architecture used by newer ESP32-C, H and P families.
In industrial practice
It supports the evolution of open tools and appears in low-power, high-performance controllers.
Related:CPU architectureXtensaULP
Intermediate
Xtensa
A configurable Cadence architecture used by the classic ESP32 and the S2 and S3 families.
In industrial practice
Its ecosystem is mature, but binaries are not interchangeable with ESP32 RISC-V devices.
Related:CPU architectureRISC-VCores
Basic
Cores
Execution units that can process tasks concurrently.
In industrial practice
Separating communication, control and interface work can improve predictability when synchronization is correct.
Basic
Clock
The CPU operating frequency, normally expressed in MHz.
In industrial practice
A higher clock does not guarantee lower latency when the network, flash or concurrent tasks are the bottleneck.
Related:CoresFreeRTOSDeep sleep
Advanced
ULP
An ultra-low-power coprocessor that can run simple tasks while the main CPU sleeps.
In industrial practice
It can monitor sensors or wake the system without keeping the entire ESP32 active.